DFT Architecture and Implementation

• Planning of Flow and Methodology Development

Scan Insertion

• Hierarchical Scan, CODEC, Test Point insertion, Core Wrapping (Intest-Extest), OCC insertion & Configuration, DRC fixes, Defining & Configuring various test modes
• Implementation of DFT for low pin count design
• Implementation of hardware for power-aware and multiple power domain design
• Implementation of support for miscellaneous tests and diagnosis support
• LBIST insertion and verification
• Logic equivalent checks
• Implementation of Security and functional safety features

ATPG Pattern Generation for Different Fault Models

• Generation of high-quality test and debug patterns for Stuck-at, Transition, Small delay defect, Cell aware Fault Model for block and top level
• Coverage analysis and improvement by reviewing test flow and design
• Improving test quality by TPI, TAT/TDV analysis and quality review for overall test program
• Pattern retargeting using IJTAG
• Simulation of test vectors across the corners

MBIST

• MBIST insertion and verification
• Implementing hardware for repair and non-repair test
• Timing and no-timing simulation
• Production pattern generation

IO Testing

• Implementation of Boundary Scan at SOC Level (1149.1)
• Loopback tests

Post Silicon Debug and ATE Support

• Test Program review
• Post Silicon Support and ATE Bring up
• Test failure diagnosis and resolution